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Network on chip and communication interface IPs for GF 12 LP+ technology

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Description

The division SSE of Fraunhofer IIS is currently looking for Network on Chip (NoC) and interface IPs for their high performance computing chiplet research project STXMOD for a proof of concept. After a successful evaluation a redesign for a commercial low volume product shall be considered. Lot 1: The SoC under development will need a configurable NoC as well as a physical communication interface compliant to the PCIe gen5 standard. For this project the Globalfoundries 12LP+ FinFET technology has been selected for MPW prototyping and later low volume production.

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